1. Field of the Invention
The present invention relates to methods for pattern defect inspection and semiconductor-device manufacturing methods involving the pattern defect inspection. In particular, the present invention relates to a method for pattern defect inspection for reticles or semiconductor wafers and a semiconductor-device manufacturing method involving the pattern defect inspection.
2. Description of the Related Art
Manufacture of semiconductor ICs (integrated circuits) requires inspection as to whether or not patterns are properly formed on reticles or semiconductor wafers as designed. Typically, such a pattern-defect inspection employs a method in which inspection patterns, such as reticle patterns or wafer patterns, are compared with a reference pattern drawn based on design data to detect differences between the inspection patterns and the reference pattern.
In the case of reticles, reticle patterns are made of chrome patterns formed on quartz substrates through photolithography and dry etching. Differences from the reference pattern are mainly due to chrome pinholes or chrome deposits produced by photolithography and dry etching.
When such a difference in pattern shape is small to an extent that does not affect the operation of a semiconductor IC, it does not substantially act as a defect. Accordingly, a permissible value for differences from the reference pattern is predetermined for the pattern-defect inspection, so that an inspection pattern is regarded as a defect when a detected pattern difference exceeds the threshold.
The term “threshold” herein refers to a value that defines inspection sensitivity for the pattern defect inspection. In order to increase the inspection sensitivity, the threshold is set to a low value, and in order to reduce the inspection sensitivity, the threshold is set to a high value.
The threshold is typically set to a value having a predetermined added margin (for increasing the inspection sensitivity) so that all of produced defects can be detected. Consequently, patterns that are supposed to be non-defective are also determined as defects and are processed, thus requiring a large amount of time to perform correction in a subsequent process. Of defects detected in this manner, defects that do not substantially act as defects are referred to as “false defects”.
Conversely, setting inspection sensitivity too low results in the failure of detecting true defects, thus reducing the yield of semiconductor ICs. Therefore, it is necessary to set appropriate inspection sensitivity for the pattern defect inspection, considering the yield, inspection time, and so on.
In general, for different reticles or even for the same reticle, influences that pattern differences have on device characteristics differ from each other depending on places where the patterns are formed; therefore, an appropriate value for inspection sensitivity to be set also varies. In many cases, the inspection sensitivity is set to the same value for all reticles used in the manufacture of the same semiconductor IC. Thus, in such cases, the inspection sensitivity must be adjusted to the inspection sensitivity of a portion requiring the highest inspection sensitivity. Thus, there is a problem in that the inspection sensitivity for other portions becomes too high.
Accordingly, a method in which a reticle is divided into multiple inspection areas and inspection sensitivities that are different from each other for the inspection areas are set has been proposed. In this case, how the inspection sensitivity for each inspection area is set is determined according to the functions of wiring patterns provided in the inspection area. Specifically, for example, as disclosed in Japanese Unexamined Patent Application Publication No. 2004-45066, a wide signal line and a narrow power line are assigned inspection sensitivities that are different from each other, considering that the likelihoods of occurrence of failures, such as line breakage, in the respective lines are significantly different from each other.
As in the example described above, with respect to patterns having very simple shapes, such as a signal line and a power line, it is possible to appropriately set inspection sensitivity. However, with respect to more complicated and smaller pattern shapes, it is difficult to set appropriate inspection sensitivity, due to problems as described below.
A majority of the aforementioned chrome pinholes or chrome deposits are caused by dust attached to the reticle surface during the pattern formation process.
Differences between inspection patterns and the reference pattern are caused by not only the above-described factors but also, for example, an excess or shortage of the amount of exposure in the photolithography, an excess or shortage of dry etching, or the like. In cases in which the differences are caused by such an excess or shortage, differences from the reference pattern also occur. For example, when the chrome layer is excessively etched, the pattern width is reduced, which results in detection of a pattern difference from the reference pattern.
As the pattern shape becomes more completed and smaller, interference due to the proximity effect and so on during exposure becomes more prominent, and consequently, the pattern difference tends to become larger.
In the known pattern-defect inspection, however, when a difference from the reference pattern is defected, a determination is made as to whether or not the detected difference exceeds a pre-set threshold without considering a cause of the occurrence of the pattern difference. As a result, there is a problem in that many false defects, which should not be to be detected, are detected. In addition, there is a problem in that a large amount of time and effort is required to subsequently remove such false defects.